The World Runs On The Transistor! It's The Mother of All Inventions. In Almost All Things Now and Into The Future. The Transistor of Things. The Brain Of All Things.
No Transistor. No Internet. No Screens Either. The Transistor Enables Us To Communicate, Collaborate, Create, Watch, Listen, Touch, Interact, Work, Live, Play, Entertain, Compute, Control, Sense, Process, Etc. AR. VR. We Are Undergoing A Digital Transformation Touching All things.
Transistor Development: What Will It Look Like Next? How Will You Develop and Evolve It?
The Process Node / Generation Illustrated. It's The "Gate Length".
1 nm = 10^-9 m or a billionth of a meter
DNA: ~2.5 nm Ø(Diameter)
Human Red Blood Cell: ~7,000 nm Ø by ~2,000 nm Thick
Human Hair: ~90,000 nm Ø
Paper Sheet: ~100,000 nm Thick
Gold Atom: ~1/3 nm Ø(Diameter)
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Transistor Type Options Beyond 3nm
Complicated and expensive technologies are being planned all the way to 2030, but it’s not clear how far the scaling roadmap will really go.
Despite a slowdown in chip scaling amid soaring costs, the industry continues to search for a new transistor type 5 to 10 years out—particularly for the 2nm and 1nm nodes.
Specifically, the industry is pinpointing and narrowing down the transistor options for the next major nodes after 3nm. Those two nodes, called 2.5nm and 1.5nm, are slated to appear in 2027 and 2030, respectively, according to the International Technology Roadmap for Semiconductors (ITRS) version 2.0. Another organization, Imec, is more aggressive with the timetable, saying that 2.5nm or thereabouts will arrive by 2024.
It’s hard to predict what will happen beyond 3nm. In fact, 3nm and beyond may never happen at all, as there are a multitude of unknowns and challenges in the arena. Perhaps chip scaling will finally run out of steam by then.
It’s even possible that today’s technology and its future iterations may provide enough performance beyond 5nm. Today’s leading-edge transistor type—the finFET—will likely extend to 5nm or 3nm, depending on how the nodes are defined. Then, at 4nm/3nm, some are moving toward a next-generation transistor technology called gate-all-around FETs, where a finFET is placed on its side and a gate is wrapped around it.
But there is also a chance the industry will require new and faster devices beyond gate-all-around. Many see a need to push the technology as far as possible, amid a revival in high-performance computing, artificial intelligence and machine learning. Autonomous driving, 5G, mobile and servers will also require more horsepower in the future. So in R&D, the industry is working on several technologies for 2.5nm and 1.5nm. At those nodes, the industry could go down the following paths:
Extend gate-all-around FETs or develop more complex versions of the technology, such as complementary FETs (CFETs) and vertical nanowire FETs.
Take existing finFETs and tweak them with new materials, creating what’s called a negative-capacitance FET (NC-FET).
Integrate devices into an advanced package.
Fig. 1: Next-gen transistor architectures. Source: Imec/ISS
There are other options as well, but it’s too early to predict a winner. “FinFETs have been a successful innovation. They still have at least one or two more generations. Beyond that, we have material changes-germanium or III-V channels. We may have gate-all-around. It’s still not clear exactly which of those ideas will eventually replace finFETs,” said Mark Bohr, senior fellow and director of process architecture and integration at Intel.
“Whether we are talking about negative-capacitance FETs, gate-all-around or III-V channels, you have to realize that modern logic products have a very demanding set of requirements,” Bohr said. “Getting high mobility is great, but you must also have low leakage. You must have low sub-threshold voltage and low power supply voltages. So right now, I’m not sure there is any technology that’s really been shown to be the winner across the board in terms of what today’s CMOS can do. We have other challenges to meet before we select a true winner.”
Why scale?
For years, the growth engine has revolved around Moore’s Law, the axiom that states transistor density would double every 18 months. Adhering to Moore’s Law, chipmakers introduced a new process every 18 months as a means to lower the cost per transistor.
Moore’s Law is viable, but it’s evolving. At each node, process cost and complexity are skyrocketing, so now the cadence for a fully scaled node has extended from 18 months to 2.5 years or longer. In addition, fewer foundry customers can afford to move to advanced nodes.
And not all are moving to leading-edge nodes. Demand for 28nm and above remains robust. And amazingly, 200mm fab demand remains strong. “We continue to see strong demand in 8-inch for 2018. And it’s coming from various applications. We see particularly strong demand in the mobile space for RF switches, the MCU, the embedded area, as well as the display area. The most challenging thing today is actually managing customers because the demand is overwhelming right now,” said Jason Wang, co-president of UMC, in a recent conference call.
Still, there are applications that require the latest processes, such as machine learning, servers and smartphones.
In another example, D2S sells a specialized high-end system based on graphics processors. The system is used for various semiconductor manufacturing applications. “So, we’re always at the very edge of utilizing available compute power,” said Aki Fujimura, chief executive of D2S. “I can say with great confidence that we’re not anywhere near about to run out of ways to use more computational power to improve semiconductor manufacturing. I’m sure that every other application domain for high-performance computing is in a similar situation. Particularly with deep learning taking off, I predict the thirst for more high-performance computing will continue to rise well beyond 7nm.”
Then there are applications that require both mature and advanced processes, such as automotive and certainly self-driving cars. “There are two different ecosystems. You have AI computations and then the sensors and controls that are in the vehicle,” said Ben Rathsack, senior member of the technical staff at TEL. “The demand for some of those older node technologies are actually increasing. And then, you have Nvidia’s processors. They may be doing AI processing. Of course, they are driving the high end.”
Meanwhile, the fab tools are ready for today’s devices. But for 2.5nm and 1.5nm, there are some gaps. To enable those nodes, the industry will require the following new technologies:
New lithography. Extreme ultraviolet (EUV) lithography is required for 7nm/5nm. Beyond 3nm, though, there may be a need for a next-generation EUV technology called high-numerical aperture (NA) EUV.
Selective processes. Chipmakers also a need a broader array of selective deposition and etch technologies, enabling vendors to deposit and remove materials in precise locations.
New interconnects schemes. The wiring schemes in chips are too congested, requiring new materials in the arena.
Then, at each node, the defects are becoming smaller and harder to find. “Lateral scaling, namely denser transistor layouts, drives the need to detect smaller defects and increases the need for design-aware inspection and review. Vertical scaling drives the need for detecting and verifying buried defects,” said Mark Shirey, vice president of marketing and applications at KLA-Tencor.
“Our problems are getting more difficult and they are more complicated. But one of the universals in this industry is that, when you have complexity and difficulty, that’s an opportunity,” said David Hemker, senior vice president and technical fellow at Lam Research, at a recent event.
Speaking on the general subject of Moore’s Law and other topics at the event, Hemker added: “We feel very bullish about being able to technically continue with Moore’s Law on almost any device. We see there are plenty of options as we want to go to 3nm and even below.”
Evolving the finFET
Today, meanwhile, chipmakers are ramping up 10nm/7nm finFETs. In finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin.
Fig. 2: FinFET vs. planar. Source: Lam Research
After 7nm, the next technology nodes are 5nm, 3nm, 2.5nm and 1.5nm, according to the ITRS roadmap. The timing of these nodes is a moving target, however, and the node names are arbitrary and don’t reflect the specs of a transistor.
So how long will the finFET last? “We believe the finFET can last to about the 5nm node. It depends, of course, on how hard you scale the gate pitch. If you relax the gate pitch a little bit, the finFET is going to last longer,” said An Steegen, executive vice president of semiconductor technology and systems at Imec. “We see the nanosheet, the elongated nanowire, is a good candidate after that.”
For some, the successor to finFETs is a next-generation technology called the lateral gate-all-around FET. Slated for 4nm and/or 3nm in 2020 or so, gate-all-around is an evolutionary step from a finFET.
The two main types of gate-all-around FETs are the nanowire FET and nanosheet FET. In nanowire FETs, tiny wires are used for the channels. Nanosheet FETs use sheet-like materials for the channels.
Fig. 3: Cross-section simulation of (a) finFET, (b) nanowire, and (c) nanosheet. Source: IBM
Gate-all-around provides more control of the gate, which improves performance and reduces leakage. “It’s this improved gate control that enables you to continue to scale the gate length,” said Mike Chudzik, managing director of technical programs at Applied Materials.
It’s possible to develop gate-all-around devices using today’s fab tools and design techniques. For example, chipmakers could still leverage an established technique called design technology co-optimization.
The idea here is to reduce the track height and cell size in a standard cell layout at each node. Standard cells are pre-defined logic elements in a design. The cells are laid out in a grid. The track defines the height of a standard cell layout. For example, 7nm might have a 6-track height cell, enabling a device with a gate-pitch of 56nm and a metal pitch of 36nm, according to Imec.
Then, 4nm/3nm involves a layout with a 5.5-4.5 track height, enabling a device with a gate pitch from 36nm to 42nm, and a metal pitch from 21nm to 24nm, according to Imec.
Fig. 4: Cell library scaling enabled by scaling boosters. Source: Imec
Based on the roadmaps, the lateral nanowire/nanosheet FET may extend from 4nm/3nm to somewhere around 2nm, meaning the technology may last for only one or two nodes.
At 2nm, the industry faces some roadblocks. In theory, a 2nm device would consist of a 3-track height layout, but this type of scheme is difficult to envision, at least for now. “You really need at least 3 tracks in order to make a normal cell,” said Diederik Verkest, a program director at Imec. “With that type of architecture, it becomes extremely challenging.”
All told, the industry may need a new solution. But chipmakers don’t want to start from scratch. Instead, they prefer to take the existing work and manufacturing technologies and evolve them.
Fig. 5: Imec’s view of transistor roadmap.
Imec proposes two options—CFETs and vertical nanowires. Slated for 2.5nm and beyond, a CFET is a more complex version of a gate-all-around device. Traditional gate-all-around FETs stack several p-type wires on top of each other. In a separate device, the transistor stacks n-type wires on each other.
In CFETs, the idea is to stack both nFET and pFET wires on each other. A CFET could stack one nFET on top of a pFET wire, or two nFETs on top of two pFET wires.
Since a CFET stacks both n- and p-type devices on each other, the transistor provides some benefits. “The main benefit is area. Area scaling brings you some benefits in power and performance,” Verkest said. “In terms of electrostatic control, a CFET would be the same as normal nanowire. They are both gate-all-around architectures.”
Other benefits are less clear. CFETs would provide an area scaling boost, but they have roughly the same transistor specs as a traditional gate-all-around device.
CFETs are more difficult to make in the fab and may require a taller structure. That, in turn, may mean higher capacitance.
Another solution is a vertical nanowire FET (VFET). A lateral gate-all-around FET stacks the wires horizontally. In contrast, VFETs stack the wires vertically. The source, gate and drain are stacked on top of each other. That means there is a gain in area.
Fig. 6: Lateral nanowire FET vs. vertical nanowire. FET Source: Imec
VFETs have some drawbacks. The VFET is an effective device to scale SRAM. But it is not a device that scales the logic cell.
VFETs are also difficult to make in the fab, but the technology has been demonstrated in the lab. At IEDM, Imec, Lam Research and KU Leuven presented a paper on the VFET with vertical nanosheets and III-V materials. In the flow, a pattern is formed on a structure using eBeam lithography. The surface is etched, forming vertical nanowires ranging from 25nm to 75nm in diameter in arrays from 1 to 100 nanowires, according to the paper.
What are NC-FETs?
There are other options. In 2008, researchers from Purdue University proposed the idea of so-called negative-capacitance FETs or NC-FETs.
Targeted for 3nm and beyond, the NC-FET isn’t a new device. Instead, an NC-FET takes an existing transistor with a high-k/metal-gate stack based on hafnium oxide. Then, the gate stack is modified with ferroelectric properties, creating a steep sub-threshold slope device well below the 60mV/decade limit.
Fig. 7: Negative capacitance FET. Source: Peter Grünberg Institute for Semiconductor Nanolelectronics
Planar devices, finFETs and even gate-all-around, can be modified with ferroelectric properties, as long as it incorporates hafnium oxide. “Essentially, a ferroelectric is like a voltage amplifier. You put one voltage on it. Because the way it interacts, it amplifies the voltage. That’s why you get this enhanced sub-threshold slope,” Applied’s Chudzik said.
Fig, 8: Schematics of NC-FET. Source: SRC, University of Nebraska-Lincoln
NC-FETs fall in the same category as tunnel FETs (TFETs), a futuristic steep sub-threshold transistor candidate. Unlike NC-FETs, though, TFETs would require a completely new structure.
NC-FETs are related to a technology called the ferroelectric FET (FeFET). Both NC-FETs and FeFETs harness the ferroelectric properties in hafnium oxide.
FeFETs and NC-FETs are different. “The most important difference is that the NC-FET is for logic and the FeFET is for memory. The NC-FET, in principle, is a logic device that does not have a nonvolatile memory. The other one, the FeFET, is a memory device that is nonvolatile,” said Stefan Müller, chief executive of Ferroelectric Memory Co. (FMC), a startup that is developing FeFETs.
In both cases, a ferroelectric material is sandwiched between two other materials and deposited into a hafnium-based gate stack using deposition. “In FeFETs, the desire is to keep this buffer between the ferroelectric and silicon bulk material as thin as possible. This has to do with data retention. The thinner the buffer layer, the better the data retention,” Müller said. “NC-FET is different. The NC-FET transistor, in principal, has no data retention. That means the requirement on this buffer layer between the ferroelectric and silicon bulk is different.”
In one example, GlobalFoundries recently presented a paper on an experimental 14nm finFET, which incorporates doped hafnia ferroelectric layers in the gate stack. GlobalFoundries called it a 14nm ferroelectric finFET. It could be classified as finFET with negative-capacitance or an NC-FET.
In a 14nm finFET, GlobalFoundries tested ferroelectric layers at thicknesses of 3nm, 5nm and 8nm. They also tested a 1.5nm undoped layer. “We find that an 8nm thick film still yields functional devices,” said Zoran Krivokapic, a senior member of the technical staff at GlobalFoundries, in the paper. “Ferroelectric devices show improved sub-threshold slopes as low as 54mV/dec. For the first time, we show that ring oscillators with ferroelectric devices can operate at frequencies similar to regular dielectrics, while improved sub-threshold slope reduces their active power.”
NC-FETs face some challenges, though. “There is a lot of promise and interest in it, but there are a lot of unanswered questions. With the gate, you have only so much volume in which to put a ferroelectric material in. The ferroelectrics are thick, 50 to 80 angstroms. That would close the gap on a modern finFET,” Applied’s Chudzik said. “The industry is already at 7nm, so they need to scale that material and still show it’s a ferroelectric. Reliability is a challenge. And then there might be some unique device design constraints due to some parasitics.”
Other solutions
IC makers are also looking for an alternative from chip scaling. One idea is to put multiple devices in an advanced package, which may provide the same functionality as a scaled device at a lower cost.
Some call this hybrid scaling or heterogeneous integration. “I don’t think people will say, ‘And now we are going to stop with device scaling and we are going to switch to hybrid scaling,'” Imec’s Steegen said. “Think about packages today and the way you stack different dies in a package. You could also see this already as a form of hybrid scaling. You could say it has started today. But we can continue to build on that road.”
What’s next? Beyond 1.5nm, the roadmap is cloudy. On Imec’s roadmap, there are several futuristic technologies, such as TFETs and spin-wave devices. 3D nanofabrics, a logic version of 3D NAND, is also a possibility.
These futuristic devices will require new tools and materials, not to mention funding.
Clearly, there are more questions than answers beyond 5nm. Perhaps gate-all-around is the answer, or researchers will stumble upon a new technology. Then, of course, today’s technology could last longer, pushing out the need for these newfangled transistors.
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Making Chips At 3nm And Beyond
Lots of new technologies, problems and uncertainty as device scaling continues.
Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that.
Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issues and the unforeseen pandemic outbreak, according to analysts. COVID-19 has slowed the momentum and impacted the sales in the IC industry.
This, in turn, is likely to push back the roadmaps beyond 3nm. Nevertheless, the current climate hasn’t stopped the semiconductor industry. Today, foundries and memory makers are running at relatively high fab utilization rates.
Behind the scenes, meanwhile, foundries and their customers continue to develop their 3nm and 2nm technologies, which are now slated for roughly 2022 and 2024, respectively. Work is also underway for 1nm and beyond, but that’s still far away.
Starting at 3nm, the industry hopes to make the transition from today’s finFET transistors to gate-all-around FETs. At 2nm and perhaps beyond, the industry is looking at current and new versions of gate-all-around transistors.
At these nodes, chipmakers will likely require new equipment, such as the next version of extreme ultraviolet (EUV) lithography. New deposition, etch and inspection/metrology technologies are also in the works.
Needless to say, the design and manufacturing costs are astronomical here. The design cost for a 3nm chip is $650 million, compared to $436.3 million for a 5nm device, and $222.3 million for 7nm, according to IBS. Beyond those nodes, it’s too early to say how much a chip will cost.
Not all designs require advanced nodes. In fact, rising costs are prompting many to explore other options, such as advanced packaging. One way to get the benefits of scaling is by putting advanced chips in a package.
Semiconductor Engineering has taken a look at what’s ahead in terms of the next transistors, fab tools, materials, packaging and photonics.
New transistors and materials
Transistors, one of the key building blocks in chips, provide the switching functions in devices. For decades, chips based on planar transistors were the most advanced devices in the market.
At 20nm, planar transistors hit the wall. In response, Intel in 2011 moved to finFETs at 22nm, followed by the foundries at 16nm/14nm. In finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin.
With finFETs, chipmakers have continued with traditional chip scaling. But finFETs are expected to run out of steam when the fin width reaches 5nm, which will occur somewhere around the 3nm node. So at 3nm, select foundries in 2022 hope to migrate to a next-generation transistor called nanosheet FETs. A nanosheet FET falls under a category called gate-all-around FETs.
A nanosheet FET is an extension of a finFET. It’s a finFET on its side with a gate wrapped around it. Nanosheets will appear at 3nm and may extend to 2nm or beyond.
Figure 1: Planar transistors vs finFETs vs nanosheet FET. Source: Samsung
There are other options on the table that also fall into the gate-all-around category. For example, Imec is developing a forksheet FET for 2nm. In forksheet FETs, both nFET and pFET are integrated in the same structure. A dielectric wall separates the nFET and pFET. This is different from existing gate-all-around FETs, which use different devices for the nFETs and pFETs.
Forksheet FETs allow for a tighter n-to-p spacing and reduction in area scaling. Imec’s 2nm forksheet has a 42nm contacted gate pitch (CPP) and a 16nm metal pitch. In comparison, nanosheets have a 45nm CPP and 30nm metal pitch.
Complementary FETs (CFETs), another type of gate-all-around device, are also an option at 2nm and perhaps beyond. CFETs consist of two separate nanowire FETs (p-type and n-type). Basically, the p-type nanowire is stacked on top of an n-type nanowire.
“The concept of CFET consists in ‘folding’ the nFET on the pFET device, which eliminates the n-to-p separation bottleneck and, as a consequence, reduces the cell active area footprint by a factor two,” said Julien Ryckaert, program director at Imec, in a recent paper.
CFETs are promising. “When people look at gate-all-around technologies, and specifically stacked complementary nanowires (CFETs) and similar technologies, they see these enabling technologies as creating an inflection point toward 3nm, 2nm and 1nm logic scaling,” said David Fried, vice president of computational products at Lam Research/Coventor. “People are reviewing the stacked nanowire landscape trajectory along with the next steps to enable that transition. This is what people are thinking might be beyond 3nm. I don’t know that anybody is defining the nodes in that space, but these technologies might enable the next scaling trajectory at 3nm and beyond.”
CFETs and related transistors have some challenges, though. “The problems are the thermal processes,” said Jeffrey Smith, senior member of the technical staff at TEL. “You need to put a lot of metals down before the high-temperature processes. So you need to identify the maximum thermal limits for the barrier metals needed between the contact and the interconnect of the CFET.”
All told, CFETs will require time to develop because today there is very little silicon learning to draw upon, and lots of problems to solve. “CFET is promising, but it’s still early,” said Handel Jones, CEO of IBS. “A big problem is that even though the gate structures are enhanced, we need to enhance the MOL and the BEOL. Otherwise, the performance enhancements are limited.”
Manufacturing chips at 2nm/1nm brings up a whole slew of new issues, and new techniques and equipment will be required across a variety of different steps. This is evident in the thin films applied during manufacturing.
“When you start getting down to layers that are less than 5nm thick in spin-coat deposits, you are susceptible to small variations in surface energy,” said James Lamb, Corporate Technical Fellow at Brewer Science. “That may be from your substrate or it may be from your material. So you really need to be perfect in your wetting and substrate surface being coated, as well as the material you’re coating with, to not have any defects. These are thin enough where the interface dynamics dominate the film formation much like in self-assembly processes, and it’s very susceptible to minor changes.”
To put this in perspective, a 1nm film may have 5 to 8 atoms of thickness. Many of these films are in the range of 30 to 40 atoms.
“Laying that down, wetting the surface, and getting the material to adhere to that surface becomes a challenge,” said Lamb. “A key driver is the cleanliness of the materials. If you have any variation in the substrate, you’re going to get an anomaly or a localized thickness variation.”
New EUV scanners
Lithography, the art of patterning tiny features on chips, helps enable chip scaling. At 3nm and beyond, chipmakers likely will require a new version of EUV lithography called high-numerical aperture EUV (high-NA EUV).
An extension of today’s EUV, high-NA EUV is still in R&D. Targeted for 3nm in 2023, the mammoth-size tool is complex and expensive.
EUV is important for several reasons. For years, chipmakers used optical-based 193nm lithography scanners in the fab. With the help of multiple patterning, chipmakers have extended 193nm lithography down to 10nm/7nm. But at 5nm, the current lithographic technologies run out of steam.
That’s where EUV fits in. EUV enables chipmakers to pattern the most difficult features at 7nm and beyond. “Using EUV at 13.5nm wavelengths should make it easier and more viable,” said Aki Fujimura, CEO of D2S.
EUV has been a difficult technology to develop. Today, though, ASML is shipping its latest EUV scanner. Using a 13.5nm wavelength with a 0.33 NA lens, the system enables 13nm resolutions with a throughput of 170 wafers per hour.
At 7nm, chipmakers are patterning the tiny features using an EUV-based single patterning approach. Single patterning EUV will extend to roughly 30nm to 28nm pitches. Beyond that, chipmakers require EUV double patterning, which is a difficult process.
“Even if we apply multiple patterning techniques to EUV, overlay will be incredibly difficult,” said Doug Guerrero, senior technologist at Brewer Science.
Double patterning EUV is still an option at 5nm/3nm and beyond if it proves to be cost-effective. But to hedge their bets, chipmakers want high-NA EUV, enabling them to continue with the simpler single-patterning approach.
A high-NA EUV scanner is complex, though. The system features a radical 0.55 NA lens capable of 8nm resolutions. Instead of a traditional lens design, the high-NA tool will use an anamorphic lens. This lens supports 8X magnification in the scan mode and 4X in the other direction. As a result, the field size is reduced by one half. So in some cases, a chipmaker would process a chip on two different masks. Then, the masks are stitched together and printed on the wafer, which is a complex process.
There are other issues. The resists for high-NA aren’t available. Fortunately, the existing EUV mask tools can be leveraged for 3nm and beyond.
The industry, however, may require EUV mask blanks with new materials. This, in turn, requires faster mask blank ion beam deposition (IBD) tools. “We are working aggressively with our key customers to release several advanced features within our IBD system design that will address 3nm and beyond,” said Meng Lee, director of product marketing at Veeco.
All told, high-NA faces several challenges. “High-NA EUV is still several years away from reaching high-volume production capabilities,” said Patrick Ho, an analyst with Stifel Nicolaus. “ASML may begin to deliver beta systems in 2021. But as EUV has taught us, beta systems do not mean that high-volume production is around the corner.”
Molecular-level processing
Today’s chips are produced using various atomic-level processing tools. One such technology, called atomic layer deposition (ALD), deposits materials one layer at a time.
Atomic layer etch (ALE), a related technology, removes targeted materials at the atomic scale. Both ALD and ALE are used in logic and memory.
The industry also is working on advanced versions of ALD and ALE for the sub-3nm nodes. Area-selective deposition, an advanced self-aligned patterning technique, is one such technology. Combining novel chemistries with ALD or molecular layer deposition (MLD) tools, selective deposition involves a process of depositing materials and films in exact places. In theory, selective deposition can be used to deposit metals on metals and dielectrics on dielectrics on a device.
Potentially, it could reduce the number of lithography and etch steps in the flow. But area-selective deposition is still in R&D amid a slew of challenges.
Another technology on the horizon is molecular layer etch (MLE). “ALE has been around since the 1990s,” said Angel Yanguas-Gil, principal materials scientist at Argonne National Laboratory. “It was plasma-based, but there have been developments for inorganic materials involving isotropic atomic-layer etching, which is where we are today. Molecular layer etch is an extension of that for hybrid organic/inorganic materials. For the semiconductor industry, it provides a way of doing isotropic reduction of materials that could be used as masks for lithography.”
For chips developed in the low single-digit nodes, one of the big problems is the selective growth of devices. Also problematic is the removal of specific materials. So anomalies that show up in chips can be removed with some kind of etch, but at these geometries any material that is left over on a wafer can cause additional problems, such as a blockage in the mask.
“The industry has been looking at block copolymers as a way of producing these tightly patterned surfaces,” said Yangaus-Gil. “When you do the block copolymer approach, you get very nice lines, but they come with a lot of roughness. The exploration of this process relies on ALD precursors. People haven’t demonstrated yet that you can selectively grow masks. But if you had to bet on the next way to go, it probably will be in that direction.”
Nearly all of the commercial efforts in the past have focused on inorganic materials, which are denser and thinner than organic materials. But as more organic materials enter into the manufacturing processes, things get more complex.
“There will be tradeoffs between the isotropic nature and the saturation value that you get for the mask release, which in this process is higher in terms of thickness, even though the material is lower density,” Yangaus-Gil said. “With MLE, what we are doing is releasing a specific bond from the surface. What you have to keep in mind is how ordered the individual layers are, and how that affects accessibility to the bond you are targeting in the MLE process.”
Process control challenges
Inspection and metrology are also important. Inspection uses various systems to find defects in chips, while metrology is the art of measuring structures.
Inspection is split into two categories—optical and e-beam. Optical inspection tools are fast, but they have some resolution limits. E-beam inspection systems have better resolution, but they are slower.
So the industry has been developing multi-beam e-beam inspection systems, which in theory could find the most difficult defects at higher speeds.
ASML has developed an e-beam inspection tool with nine beams. However, chipmakers want a tool with a multitude of beams to speed up the process. It’s unclear if the industry will ever ship these tools. The technology still faces a number of challenges.
Metrology also faces some challenges. Today, chipmakers use various systems, such as CD-SEMs, optical CD and others, to measure structures. CD-SEMs take top-down measurements. Optical CD systems use polarized light to characterize structures.
A decade ago, many thought CD-SEMs and OCD would run out of steam. So the industry accelerated the development of several new metrology types, including an X-ray metrology technology called critical-dimension small-angle X-ray scattering (CD-SAXS). CD-SAXS uses variable-angle transmission scattering from a small beam size to provide the measurements. The X-rays have a wavelength less than 0.1nm.
It’s a non-destructive technique. “CD-SAXS conceptionally is a very simple measurement. An X-ray source sends a focused beam of X-rays through a sample with a periodic nanostructure and an X-ray camera takes an image of the scattered X-rays. The measurement is then repeated for a series of incident angles,” said Joseph Kline, a materials engineer at NIST. “The periodicity results in single-crystal scattering similar to what is obtained in protein crystallography. The scattering pattern can then be inversely solved to obtain the average shape of the electron density distribution of the periodic structure. The scattering calculation is a Fourier transform, so it is computationally easy for most structures. CD-SAXS can solve for CDs, disorder in the CD, and differences in electron density between layers (which can be related to composition). The main advantages of CD-SAXS over conventional OCD are that the optical constants are atomic properties independent of size, the small wavelength gives higher resolution and avoids many of the parameter correlation issues that OCD has, and the calculation is much simpler. CD-SAXS can also measure buried structures and optically opaque layers.”
Over the years, several entities have demonstrated promising results with CD-SAXS. In some cases, though, the X-rays are generated by a large synchrotron storage ring at an R&D facility.
This is impractical for a fab. For a fab tool, CD-SAXS requires compact X-ray sources. Several companies sell these tools, mostly for R&D. Intel, Samsung, TSMC and others have CD-SAXS tools in the lab.
The problem with fab-based CD-SAXS is that the X-ray source is limited and slow, which impacts throughput. “CD-SAXS gives you phenomenal profiles. Because it penetrates through the substrate, you can see layers of different materials,” said Dan Hutcheson, CEO of VLSI Research. “It’s a scatterometry-type technology like optical scatterometry, but it’s slow.”
Cost is also an issue. “It’s probably 5X or 10X more expensive. The cost-of-ownership is high compared to optical,” said Risto Puhakka, president of VLSI Research.
So chipmakers aren’t expected to insert CD-SAXS in the in-line monitoring flow for some time, at least for logic. “We typically forecast five years out,” Puhakka said.
CD-SAXS is making progress in memory. Today, in R&D, memory makers are using the technology to characterize hard masks and high-aspect ratio structures.
“For memory, the structures are deep. The scattering is good, so there is a clear roadmap to ~1 minute or less per site,” said Paul Ryan, director of product management at Bruker. “For logic, the technique is still in the concept phase, and there are expected to be challenges for the X-ray intensity.”
Fortunately, CD-SEM and OCD have extended further than previously thought and are being used today. Other X-ray metrology types are also used. But will they extend forever?
Packaging shifts
IC scaling, the traditional way of advancing a design, relies on shrinking different chip functions at each node and packing them onto a monolithic die. But IC scaling is becoming too expensive for many, and the performance and power benefits are diminishing at each node.
“From an economic standpoint, how many companies can afford silicon at the bleeding edge nowadays? That number is shrinking,” said Walter Ng, vice president of business management at UMC. “For the very, very high performance markets, there is always going to be that need. But in the supply chain, from a volume standpoint, the chasm is opening up in the middle. The very leading edge needs 7, 5 and maybe 3nm someday. But everyone else has slowed down quite a bit.”
While scaling remains an option for new designs, many are searching for alternatives like advanced packaging. Chiplets is another form of heterogenous integration.
Packaging is becoming more a viable option for several reasons. For example, while area is critical, particularly in AI applications where the speed of a chip depends on highly redundant arrays of processing elements and accelerators, the biggest benefits at each new node are derived from architectural changes and hardware-software co-design. It takes longer for a signal to travel from one end of a large chip to another over skinny wires than it does to travel vertically to another die using a high-speed interface.
This has prompted packaging houses and foundries to further improve the speed of packaged devices by improving the connections between devices, and improving the density of the packages themselves.
TSMC’s push to embed chiplets inside a package at the front-end-of-the-line (FEOL) is a case in point. The foundry plans to use advanced hybrid bonding techniques for what it calls system on integrated chips (SoIC).
That will be even faster than connecting chips together using a silicon interposer, which today is the state-of-the-art for this kind of approach. But silicon interposers also can be used as waveguides for photonics, both in-package and between packages, which adds yet another option for this approach.
“Right now, you see fiber within a server farm, which is east-west traffic,” said Rich Rice, senior vice president of business development at ASE. “You’re going to see the backplanes replaced. The fiber is not going through a module but directly to the server, and eventually to the package that the switch is on. It still has a lot of evolution to go, but we’ll see companies out there try to jump in to do the latest stuff sooner rather than later. That will accelerate the application of photonics. It will have more bandwidth, and it will get cheaper as we start to see more high-volume solutions.”
The advantage of light is that it requires less power than sending an electric signal over copper wires. “It’s still a way out in the future, but there are companies working on interposers that transmit light,” Rice said. “After that, you can interface with the chip with that, and it’s just a matter of getting those light signals into the side of the package.”
This is easier said than done, of course. Optical signals will drift as heat rises, so filters need to be calibrated to account for that drift. In addition, they can be interrupted by sidewall roughness in the waveguides. On the other hand, packaging with light is no longer just a distant research project.
There are other advantages in advanced packaging. Analog circuits can be developed at whatever node is ideal, and they can be re-used repeatedly without worrying about shrinking those devices.
In addition, the industry continues to make improvements in packaging for power semiconductors. In silicon carbide (SiC), for example, vendors integrate SiC power MOSFETs and other components in a power module. SiC itself has a higher breakdown field and a higher thermal conductivity than silicon.
Fig. 2: SiC MOSFET. Source: Cree
“What we and others are working on is how to optimize that module to take full advantage of silicon carbide. You have to know what you’re doing with a power module,” said John Palmour, CTO of Cree, in a recent interview. “Silicon carbide switches so fast versus silicon. There’s a lot of things you need to do within the package to actually get the performance out of it. In other words, if you use standard power module designs that are used for silicon, you’re only going to get about half of the performance you’re entitled to with SiC.”
Conclusion
The migration to 3nm will happen, although it might take longer than expected. The same is true for 2nm.
Beyond that, it’s unclear what will happen at 1nm. CFETs might be the way to go. On the other hand, chip scaling may end, or it may be limited to small high-performance, highly-specific chips or chiplets that require extremely high density.
In the near term, though, there is room for multiple technologies because no single technology can handle all applications.
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